Field of the Invention
The invention relates in general to a chip packaging structure, and more particularly to a chip packaging structure that disposes a passive component in a chip.
Description of the Related Art
As semiconductor technologies continue to progress, various circuit components included in an integrated circuit can be manufactured within the same chip, in a way that not only the operational efficiency is increased but also the volume of the integrated circuit can be reduced. However, conventionally, passive components in an integrated circuit require a larger volume in order to achieve expected functions. By manufacturing such passive components in a chip, an excessive large part of the volume of the chip may be occupied, leading to increased material costs required for manufacturing the chip as well as issues of inconsistent quality and characteristics of the passive components manufactured in the chip. Thus, current passive components are usually separately manufactured from the chip, and the two are then integrated in the same packaging structure through a packaging process.
In a conventional chip packaging structure, as passive components and a chip are separately disposed on a carrier board, the passive components can only be electrically connected to an integrated circuit through conductive lines and metal lines on the carrier board. In addition, due to fabrication process limitations, a certain gap needs to be kept between the passive components and the chip to prevent collisions between the passive components and the chip during die bonding. As a result, the resistance/capacitance loading effect may be too high, hence causing unsatisfactory operational efficiency of the integrated circuit.
Therefore, there is a need for a chip packaging structure for enhancing the operational efficiency of an integrated circuit.